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Interpret
as INPUT_SYNC_BYPASS
Description
There is a 2-flipflop synchronizer on each GPIO input, which protects
PIO logic from metastabilities. This increases input delay, and for fast
synchronous IO (e.g. SPI) these synchronizers may need to be bypassed.
Each bit in this register corresponds to one GPIO.
0 -> input is synchronized (default)
1 -> synchronizer is bypassed
If in doubt, leave this register as all zeroes.